High Level Synthesis (HLS) webinar for high performance digitizers

High Level Synthesis (HLS) webinar for high performance digitizers

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Learn the basics of how HLS helps simplify FPGA firmware development for high-performance digitizers

at your place: Tuesday 27 September 2022

Time: 10:00 PDT | 1:00 pm EDT

Duration: 30 minutes

Learn more about the basics of the digitizer

Join Teledyne SP Devices for an introductory webinar on HLS in the context of high performance digitizers.

Topics covered in this webinar:

  • Advantages of integrated FPGA signal processing
  • FPGA architecture and development basics
  • Programming languages ​​and development tools
  • Areas of application and examples of signal processing

Who Should Attend? Developers who want to learn more about the possibilities and benefits of digital signal processing built into high-performance digitizers.

What will the participants learn? An introduction to FPGA development for high performance digitizers.

Announcer: Thomas Elter, Senior Field Applications Engineer

Register below to attend the webinar